Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware description language is a language used to describe a digital system: for example, a network switch, a microprocessor or a memory or a simple flip-flop. This just means that, by using a HDL, one can describe any (digital) hardware at any level.

IEEE Verilog Projetcs 2019-20

S.No
Code
Title
Category
1
LMTVL01
An efficient Verilog architecture for Data Encryption Standard and its FPGA implementation
Verilog 2019-2020
Abstract   
2
LMTVL02
An efficient booth multiplier using probabilistic approach
Verilog 2019-2020
Abstract      
3
LMTVL03
High speed and energy efficient carry skip adder operating under a wide range of supply voltage levels
Verilog 2019-2020
Abstract      
4
LMTVL04
Approximate hybrid high radix encoding for energy efficient inexact multipliers
Verilog 2019-2020
Abstract      
5
LMTVL05
Hybrid LUT/Multiplexer FPGA logic architectures
Verilog 2019-2020
Abstract   
6
LMTVL06
High speed and low power Verilog architecture for inexact speculative adder
Verilog 2019-2020
Abstract   
7
LMTVL07
A reconfigurable LDPC decoder optimized for 802.11 n/ac applications
Verilog 2019-2020
Abstract   
8
LMTVL08
Algorithm and Verilog architecture design of proportionate type LMS adaptive filters for sparse system identification
Verilog 2019-2020
Abstract   
9
LMTVL09
Implementation of a PID control PWM module on altera DE0 kit using FPGA
Verilog 2019-2020
Abstract   
10
LMTVL10
Extending 3-bit burst error correction codes with quadruple adjacent error correction
Verilog 2019-2020
Abstract   
11
LMTVL11
Verilog architecture of radix-2/4/8 SISO decoder for turbo decoding at multiple data rates
Verilog 2019-2020
Abstract   
12
LMTVL12
A two speed radix-4 serial parallel multiplier
Verilog 2019-2020
Abstract   
13
LMTVL13
Approximate radix-8 booth multipliers for low power and high performance operation
Verilog 2019-2020
Abstract   
14
LMTVL14
Approximate reverse carry propagate adder for energy efficient DSP applications
Verilog 2019-2020
Abstract   
15
LMTVL15
Division circuit using reversible logic gates
Verilog 2019-2020
Abstract   
16
LMTVL16
A scheme to design concurrent error detection techniques for the FFT implemented in SRAM based FPGA
Verilog 2019-2020
Abstract   
17
LMTVL17
TOSAM: An energy efficient truncation and rounding based scalable approximate multiplier
Verilog 2019-2020
Abstract   
18
LMTVL18
Design and analysis of approximate redundant binary multiplier
Verilog 2019-2020
Abstract   
19
LMTVL19
An ALU protection methodology for soft processor on SRAM based FPGAs
Verilog 2019-2020
Abstract   
20
LMTVL20
A comparison of dual modular redundancy and concurrent error detection in FIR filters implemented in SRAM based FPGA
Verilog 2019-2020
Abstract   
21
LMTVL21
Fast AES implementation a high throughput bitsliced approach
Verilog 2019-2020
Abstract   
22
LMTVL22
An asynchronous mesh NoC based booth multiplication
Verilog 2019-2020
Abstract   
23
LMTVL3
An FPGA based phase measurement system
Verilog 2019-2020
Abstract   
24
LMTVL24
Low power approximate multipliers using encoded partial products and approximate compressors
Verilog 2019-2020
Abstract   
25
LMTVL25
A reconfigurable memory based fast Verilog architecture for computation of the histogram
Verilog 2019-2020
Abstract   
26
LMTVL26
Double MAC on a DSP boosting the performance of convolution neural networks on FPGA
Verilog 2019-2020
Abstract   
27
LMTVL27
A high performance and energy efficient FIR adaptive filter using approximate distributed arithmetic circuits
Verilog 2019-2020
Abstract   
28
LMTVL28
Multichannel filters for wireless networks lookup table based efficient implementation
Verilog 2019-2020
Abstract   
29
LMTVL29
Fast Montgomery modular multiplier for RSA cryptosystem
Verilog 2019-2020
Abstract   
30
LMTVL30
Dual channel multiplier for piecewise polynomial function evaluation for low power 3-D graphics
Verilog 2019-2020
Abstract   
31
LMTVL31
Efficient shift add implementation of FIR filters using variable partition hybrid form structures
Verilog 2019-2020
Abstract   
32
LMTVL32
Reconfigurable RO path delay sensor
Verilog 2019-2020
Abstract   
33
LMTVL33
Approximate sum of products design based on distributed arithmetic
Verilog 2019-2020
Abstract   
34
LMTVL34
Fastest FFT architecture: breaking the barrier of 100 GS/s
Verilog 2019-2020
Abstract