IEEE VLSI(Verilog) Projects 2016-17

S.No
Code
Title
Category
1
LMTVLSI01
A 5.8-GHz Wideband TSPC Divide-by-16 17 Dual Modulus Prescaler
VLSI 2016-2017
Abstract   
2
LMTVLSI02
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
VLSI 2016-2017
Abstract      
3
LMTVLSI03
A Low-Cost Low-Power Ring Oscillator-based Truly Random Number Generator for Encryption on Smart Cards
VLSI 2016-2017
Abstract      
4
LMTVLSI04
A Modified Partial Product Generator for Redundant Binary Multipliers
VLSI 2016-2017
Abstract      
5
LMTVLSI05
A New Fast and Area-Efficient Adder-Based Sign Detector for RNS
VLSI 2016-2017
Abstract   
6
LMTVLSI06
A New Paradigm of Common Sub expression Elimination by Unification of Addition and Subtraction
VLSI 2016-2017
Abstract   
7
LMTVLSI07
A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders
VLSI 2016-2017
Abstract   
8
LMTVLSI08
A Scalable Approximate DCT Architectures for Efficient HEVC Compliant Video Coding
VLSI 2016-2017
Abstract   
9
LMTVLSI09
A Single Ended With Dynamic Feedback Control T Sub threshold SRAM Cell
VLSI 2016-2017
Abstract   
10
LMTVLSI10
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis
VLSI 2016-2017
Abstract   
11
LMTVLSI11
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
VLSI 2016-2017
Abstract   
12
LMTVLSI12
CORDIC II A New Improved CORDIC Algorithm
VLSI 2016-2017
Abstract   
13
LMTVLSI13
Design and simulation of Turbo encoder in quantum-dot cellular automata
VLSI 2016-2017
Abstract   
14
LMTVLSI14
Design for Testability of Sleep Convention Logic
VLSI 2016-2017
Abstract   
15
LMTVLSI15
Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
VLSI 2016-2017
Abstract   
16
LMTVLSI16
Designing Tunable Sub threshold Logic Circuits Using Adaptive Feedback Equalization
VLSI 2016-2017
Abstract   
17
LMTVLSI17
Efficient Circuit for Parallel Bit-Reversal
VLSI 2016-2017
Abstract   
18
LMTVLSI18
Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks
VLSI 2016-2017
Abstract   
19
LMTVLSI19
Graph-Based Transistor Network Generation Method for Super gate Design
VLSI 2016-2017
Abstract   
20
LMTVLSI20
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
VLSI 2016-2017
Abstract   
21
LMTVLSI21
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
VLSI 2016-2017
Abstract   
22
LMTVLSI22
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations
VLSI 2016-2017
Abstract   
23
LMTVLSI3
Hybrid LUT Multiplexer FPGA Logic Architectures
VLSI 2016-2017
Abstract   
24
LMTVLSI24
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
VLSI 2016-2017
Abstract   
25
LMTVLSI25
Low-Complexity First-Two-Minimum-Values Generator for Bit-Serial LDPC Decoding
VLSI 2016-2017
Abstract   
26
LMTVLSI26
Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST
VLSI 2016-2017
Abstract   
27
LMTVLSI27
Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
VLSI 2016-2017
Abstract   
28
LMTVLSI28
Low-Power Programmable PRPG With Test Compression Capabilities
VLSI 2016-2017
Abstract   
29
LMTVLSI29
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
VLSI 2016-2017
Abstract   
30
LMTVLSI30
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design
VLSI 2016-2017
Abstract   
31
LMTVLSI31
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
VLSI 2016-2017
Abstract   
32
LMTVLSI32
Multiplier less Unity-Gain SDF FFTs
VLSI 2016-2017
Abstract   
33
LMTVLSI33
Reverse Converter Design via Parallel-Prefix Adders Novel Components, Methodology, and Implementations Turbo Decoders
VLSI 2016-2017
Abstract   
34
LMTVLSI34
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications
VLSI 2016-2017
Abstract   
35
LMTVLSI35
Timing Error Tolerance in Small Core Designs for SoC Applications
VLSI 2016-2017
Abstract   
36
LMTVLSI36
Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes
VLSI 2016-2017
Abstract